Since I started this article series, I’ve had the awesome opportunity to have my ideas (well, some of the early articles at least) reviewed by person(s) who deal with the actual infrastructure of storage systems day in, day out. The benefit of such peer review is that you get to learn at the symbolic “feet” of the masters and discover flaws, omissions, and understated features that need to be understood and incorporated. This post is dedicated to some of those discussions and, where applicable, my understanding of how the FSS either incorporates or misses the boat.
In the previous two articles on the Future Storage System (FSS), I took a general look at a basic storage system architecture (Part 1) and then went a bit deeper into some of the more interesting bits of that system from a platform standpoint (Part 2). In this article, I want to dive a bit deeper into how I envision nodes to be building blocks for additional capabilities and processing directives. I will be referencing the image below as part of this article.
So, in my article yesterday, I gave a global view of a very simple storage system for the future. Since I LOVE this type of conjecture and theoretics (is that a word?), I decided to take this a step further and flesh out some of the other intricacies of the design. Check out the image below and then click through to read the rest.
Is it just me or have we been waiting for this for a while? 😉 Today is officially the EMC Clariion CX4 public GA (general availability) date. Good news: they’re shipping TODAY! No paper launches, folks…this is immediate availability. The other good news: you get to do more with your storage; faster, cheaper, stronger, more flexible, etc. Let me rip through some highlights for you:
a.) Cache and SP Processor increases. Across the board, processor “speeds” and cache sizes have been increased. Now, this may appear somewhat odd in that the CX4-120, for example, only has two dual core 1.2ghz processors, but, when you consider that the onboard L2 cache is greater in size (and Woodcrest processors were HANDILY more powerful than the older Nocona Xeons), it actually has more innate processing power than the previous generation processors. Cache sizes, when coupled with the 64 bit FLARE OS for the array, allow for better allocation and utilization within the array.
Just thought I’d introduce myself as the latest blog persona to float into the Inter-ether. The name is Dave Graham and I’m an avid storage fan. Coming from a background of business analytics, social psychology (more on that later), and IT consultancy, I’m glad to finally be “at home” with an employer who challenges my concepts of “good” storage and pushes me to become the best I can be. Whew! That was an exceptionally long-winded intro but, captures who I am. Moving forward, I hope to be able to indulge you in two of my distinct passions: high-speed, low latency interconnects for storage (Hypertransport/LDT, Infiniband, PCIe, et al.) and *drumroll please* CAS (especially as it relates to EMC Centera. I welcome all feedback as I pursue these passions and, hopefully, along the way, we can have serious dialogue.
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