Future Storage Systems: Part 3b – I/O Expansion Node

October 10, 2008

In Part 3a, we discussed the possibility of a purpose-driven Compute Node based on the Torrenza initiative for the Future Storage system.  This expansion node made use of Hypertransport as a “glue” between the base storage compute node and the expansion node (of computation or I/O flavours) that could be added.  The advantages of that topology were simple:  hot add support for additional processing power, additional I/O bandwidth within the system, and additional computing power for the array OS (which we’ll cover in a later article).  In this overview, we’ll take a look at another variation on an expansion node: an I/O expansion node that will add additional front-end ports and/or functionality to the base system.  We will be referencing the diagram below. (Apologies in advance for the image shearing off in the lower right hand corner).

Hypertransport I/O Expansion Topology

Hypertransport I/O Expansion Topology

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Future Storage Systems: Part 3a – Node Expansion Overview

October 9, 2008

In the previous two articles on the Future Storage System (FSS), I took a general look at a basic storage system architecture (Part 1) and then went a bit deeper into some of the more interesting bits of that system from a platform standpoint (Part 2).  In this article, I want to dive a bit deeper into how I envision nodes to be building blocks for additional capabilities and processing directives.  I will be referencing the image below as part of this article.

Hypertransport Node Expansion (detailed)

Hypertransport Node Expansion (detailed)

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Why wouldn’t the following work? (Future Storage System: Part 1)

October 7, 2008

So, I’ve been toying around with this in my mind for some time.  Essentially, I’ve tried to understand the basic “Storage Processor” limitation of current storage systems and propose an admittedly simplistic design to get around some of the difficulties.  The biggest hurdle, in my mind, is to have cache coherency, low latency memory access to other nodes in a “cluster,” and have a communications “bus” between nodes that is extensible (or at least will grow bandwidth with more devices on the signal chain).  Staring at that problem, then, look at the image below.

A case for Hypertransport connected nodes...

A case for Hypertransport connected nodes...

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Something Cool! (AMD + Tyan content)

July 30, 2008
Official logo of the 2008 Summer Olympic GamesImage via Wikipedia

One of the things I do in my spare time is develop rendering systems for a client in another country.  The cool thing about this is that I’m able to use cutting-edge AMD processors and platforms from Tyan and nVidia in order to accomplish these goals.

I just found out that one of my rendering systems was used to process the following Coca-Cola commercial for the 2008 Summer Olympics!!!  There is a little special trick to this system, however, that warrants a closer look. Read the rest of this entry »


Fun with nVidia’s Hybrid SLI

June 14, 2008
Nvidia SLI Logo

Image via Wikipedia

It’s always fun to bring in “extra-curricular” stuff that I do to my day job.  That being said, this one is strictly outside the scope of day-to-day work.  I recieved a very interesting bit of technology from nVidia that is designed to demo out their Hybrid SLI platform.  What is Hybrid SLI, you ask?

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