Future Storage Systems: A pause in workflow

October 17, 2008

Since I started this article series, I’ve had the awesome opportunity to have my ideas (well, some of the early articles at least) reviewed by person(s) who deal with the actual infrastructure of storage systems day in, day out.  The benefit of such peer review is that you get to learn at the symbolic “feet” of the masters and discover flaws, omissions, and understated features that need to be understood and incorporated.  This post is dedicated to some of those discussions and, where applicable, my understanding of how the FSS either incorporates or misses the boat.

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Future Storage Systems: Part 3a – Node Expansion Overview

October 9, 2008

In the previous two articles on the Future Storage System (FSS), I took a general look at a basic storage system architecture (Part 1) and then went a bit deeper into some of the more interesting bits of that system from a platform standpoint (Part 2).  In this article, I want to dive a bit deeper into how I envision nodes to be building blocks for additional capabilities and processing directives.  I will be referencing the image below as part of this article.

Hypertransport Node Expansion (detailed)

Hypertransport Node Expansion (detailed)

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Why wouldn’t the following work? (Future Storage System: Part 1)

October 7, 2008

So, I’ve been toying around with this in my mind for some time.  Essentially, I’ve tried to understand the basic “Storage Processor” limitation of current storage systems and propose an admittedly simplistic design to get around some of the difficulties.  The biggest hurdle, in my mind, is to have cache coherency, low latency memory access to other nodes in a “cluster,” and have a communications “bus” between nodes that is extensible (or at least will grow bandwidth with more devices on the signal chain).  Staring at that problem, then, look at the image below.

A case for Hypertransport connected nodes...

A case for Hypertransport connected nodes...

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Snoop Filters and the Tyan S5397

September 26, 2008

Just to add to the ever-growing information data base on the excellent Tyan S5397.

If you seem to be having problems with reported memory bandwidth in your favourite worthless synthetic benchmark or reality-based simulation workload, try disabling the Snoop Filter in the bios.

Remember, the Intel Xeon processors use a different set of prefetch schedulers than standard “consumer” level parts, so, this can also affect workload.

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Something Cool! (AMD + Tyan content)

July 30, 2008
Official logo of the 2008 Summer Olympic GamesImage via Wikipedia

One of the things I do in my spare time is develop rendering systems for a client in another country.  The cool thing about this is that I’m able to use cutting-edge AMD processors and platforms from Tyan and nVidia in order to accomplish these goals.

I just found out that one of my rendering systems was used to process the following Coca-Cola commercial for the 2008 Summer Olympics!!!  There is a little special trick to this system, however, that warrants a closer look. Read the rest of this entry »


Fun with nVidia’s Hybrid SLI

June 14, 2008
Nvidia SLI Logo

Image via Wikipedia

It’s always fun to bring in “extra-curricular” stuff that I do to my day job.  That being said, this one is strictly outside the scope of day-to-day work.  I recieved a very interesting bit of technology from nVidia that is designed to demo out their Hybrid SLI platform.  What is Hybrid SLI, you ask?

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