So, in my article yesterday, I gave a global view of a very simple storage system for the future. Since I LOVE this type of conjecture and theoretics (is that a word?), I decided to take this a step further and flesh out some of the other intricacies of the design. Check out the image below and then click through to read the rest.
So, I’ve been toying around with this in my mind for some time. Essentially, I’ve tried to understand the basic “Storage Processor” limitation of current storage systems and propose an admittedly simplistic design to get around some of the difficulties. The biggest hurdle, in my mind, is to have cache coherency, low latency memory access to other nodes in a “cluster,” and have a communications “bus” between nodes that is extensible (or at least will grow bandwidth with more devices on the signal chain). Staring at that problem, then, look at the image below.
Is it just me or have we been waiting for this for a while? 😉 Today is officially the EMC Clariion CX4 public GA (general availability) date. Good news: they’re shipping TODAY! No paper launches, folks…this is immediate availability. The other good news: you get to do more with your storage; faster, cheaper, stronger, more flexible, etc. Let me rip through some highlights for you:
a.) Cache and SP Processor increases. Across the board, processor “speeds” and cache sizes have been increased. Now, this may appear somewhat odd in that the CX4-120, for example, only has two dual core 1.2ghz processors, but, when you consider that the onboard L2 cache is greater in size (and Woodcrest processors were HANDILY more powerful than the older Nocona Xeons), it actually has more innate processing power than the previous generation processors. Cache sizes, when coupled with the 64 bit FLARE OS for the array, allow for better allocation and utilization within the array.